GENERAL DESCRIPTION The PCE84C882 is the enhanced version of the PCE84C886 having all the features of this device but in addition provides: • Two dedicated power pins for the PLL oscillator circuit • A choice of two mask-programmable prescaler values for the PLL oscillator • A higher frequency OSD clock - up to 20 MHz • An improved edge-sensitive counter (T3). FEATURES General • CMOS 8-bit CPU (enhanced 8048 CPU) with 8 kbytes system ROM and 192 bytes system RAM • One 8-bit timer/event counter (T1) and one 8-bit counter triggered by external input (T3) • Four single level vectored interrupt sources: external (INTN), counter/timer, I2C-bus and VSYNCN • 2 directly testable inputs T0 and T1 • On-chip oscillator clock frequency: 1 to 10 MHz • On-chip Power-on-reset with low power detector • Twelve quasi-bidirectional I/O lines, configuration of each I/O line individually selected by mask option • Idle and Stop modes for reduced power consumption • Operating temperature: −25 to +85 °C • Operating voltage: 4.5 to 5.5 V • Package: SDIP42. Special • Master-slave I2C-bus interface • Three 6-bit Pulse Width Modulated outputs (PWM4; PWM6 and PWM7) • Four 7-bit Pulse Width Modulated outputs (PWM0 to PWM3) • One 14-bit Pulse Width Modulated output (PWM8) • One 4-bit ADC channel • 14 derivative I/O ports. OSD • Maximum dot frequency (fOSD): 20 MHz (see Section 20 for details) • Display RAM: 64 × 10 bits • Display character fonts: 62 + 2 special reserved codes • Character matrix: 12 × 18 (no spacing between characters) • 4 character sizes: 1H/1V, 1H/2V, 1H/3V and 1H/4V • 64 Horizontal starting positions (4 dots for each step) • 64 Vertical starting positions (4 scan lines for each step) • Vertical jumping cancelling circuit • Spacing between character rows: 0, 4, 8 and 12 scan lines • Foreground colours: 8 on a character-by-character basis • Background colours: 8 on a word-by-word basis • Background/shadowing modes: 4 modes available, No background, North shadowing, Box shadowing and Frame shadowing (raster blanking) on a frame basis • On-chip Phase-Locked Loop (PLL) oscillator (auto-sync with Hsync) with programmable oscillator for On Screen Display (OSD) function • Character blinking frequency: programmable using fVsync divisors of 16, 32, 64 and 128; on a frame basis • Character blinking ratios: 1 : 1, 1 : 3 and 3 : 1 • Programmable active level polarities of VSYNCN, HSYNCN, R, G, B and FB • Flexible display format by using Carriage Return Code • Auto display RAM address (DCRAR) incremented after write operation to the Character Data Register (DCRCR) • VSYNCN generates an interrupt (enabled by software) when VIEN is active.
|