FEATURES LINE INTERFACE • Each link can be configured as T1, E1 or J1 • Supports T1/E1/J1 long haul/short haul line interface • HPS for 1+1 protection without external relays • Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024 Hz • Selectable internal line termination impedance: 100 Ω (for T1), 75 Ω / 120 Ω (for E1) and 110 Ω (for J1) • Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding • Provides T1/E1/J1 short haul pulse templates, long haul LBO (per ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template • Supports G.772 non-intrusive monitoring • Supports T1.102 line monitor • Transmit line short-circuit detection and protection • Separate Transmit and Receive Jitter Attenuators (2 per link) • Indicates the interval between the write pointer and the read pointer of the FIFO in JA • Loss of signal indication with programmable thresholds according to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1) • Supports Analog Loopback, Digital Loopback and Remote Loopback • Each receiver and transmitter can be individually powered down FRAMER • Each link can be configured as T1, E1 or J1 • Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY-000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704) and un-framed mode • Supports T1/J1 Super Frame and Extended Super Frame, T1 Digital Multiplexer and Switch Line Carrier - 96, E1 CRC Multi-frame and Signaling Multi-frame • Signaling extraction/insertion for CAS and RBS signaling • Provides programmable system interface supporting MitelTM STbus, AT&TTM CHI and MVIP bus, 8.192 Mb/s multiplexed bus and 1.544 Mb/s or 2.048 Mb/s non-multiplexed bus • Three HDLC controllers per link with separate 128-byte transmit and receive FIFOs per controller • Supports Signaling System #7 (SS7) • Programmable bit insertion and bit inversion on per channel/ timeslot basis • Provides Bit Oriented Message (BOM) generation and detection • Provides Automatic Performance Report Message (APRM) generation • Detects and generates alarms (AIS, RAI) • Provides performance monitor to count Bipolar Violation error, Excess Zero error, CRC error, framing bit error, far end CRC error, out of frame and change of framing alignment position • Supports System Loopback, Payload Loopback, Digital Loopback and Inband Loopback • Detects and generates selectable PRBS and QRSS CONTROL INTERFACE • Supports Serial Peripheral Interface (SPI) microprocessor and parallel Intel/Motorola non-multiplexed microprocessor interface • Global hardware and software reset • Two general purpose I/O pins • Per link power down GENERAL • Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz) (0<N<5) • JTAG boundary scan • 3.3 V I/O with 5 V tolerant inputs • Low power consumption (Typical 450 mW) • 3.3 V and 1.8 V power supply • 208-pin PBGA package APPLICATIONS • C.O, PABX, ISDN PRI • Wireless Base Stations • T1/E1/J1 ATM Gateways, Multiplexer • T1/E1/J1 Access Networks • LAN/WAN Router • Digital Cross Connect • SONET/SDH Add/Drop Equipment
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