GD25Q80C / GigaDevice Semiconductor (Beijing) Inc.

GD25Q80C Datasheet with Chat AI

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Part No.	GD25Q80C
Manufacturer	GIGADEVICE
Size	1Mb
Pages	67 pages
Description	3.3V Uniform Sector Dual and Quad Serial Flash

Datasheet Summary with AI

1. Overview & Functionality

️· Device Type: Uniform Sector Flash Memory
️· Quad Mode: Supports quad operation via the QE bit.

2. Key Features

️· Status Register Protection (SRP): Offers different methods of protecting the status register:
- Software Protection (Default): Writeable after a Write Enable command.
- Hardware Protection: Locked when WP# (Write Protect) is low.
- Hardware Unprotected: Writeable when WP# is high.
- Power Supply Lock-Down: Requires power cycle to unlock.
- One-Time Programmable (OTP): Permanently locked. (Special order)
️· Block Protection (BP4-BP0): Define protected memory areas against Program/Erase commands. Their behavior is dependent on the CMP bit.
️· CMP Bit: Used in conjunction with the BP bits to control protection behavior.
️· QE Bit: Enables Quad mode and controls the state of WP# and HOLD# pins. Default is 0.
️· LB Bit (OTP): Locks the Security Registers. Once set, they are read-only.
️· HPF Bit: Indicates High Performance Mode status.
️· SUS Bit: Indicates if an Erase/Program Suspend command has been executed.
️· WIP Bit: Indicates if the device is busy performing a program, erase, or write status register operation.
️· WEL Bit: Indicates the status of the internal Write Enable Latch.

3. Status Register Details

Bit Name Description

S15 SUS Erase/Program Suspend status

S14 CMP CMP bit. Affects block protection behavior.

S13 HPF High Performance Flag. Indicates High Performance Mode.

S12 Reserved Reserved bit.

S11 Reserved Reserved bit.

S10 LB One-Time Programmable lock for Security Registers.

S9 QE Quad Enable. Controls Quad mode and WP#/HOLD# pins.

S8 SRP1 Status Register Protection Bit 1.

S7 SRP0 Status Register Protection Bit 0.

S6 BP4 Block Protect bit 4.

S5 BP3 Block Protect bit 3.

S4 BP2 Block Protect bit 2.

S3 BP1 Block Protect bit 1.

S2 BP0 Block Protect bit 0.

S1 WEL Write Enable Latch.

S0 WIP Write In Progress.

4. Important Considerations & Notes:

️· Special Order Features: One-Time Programmable (OTP) protection and Power Supply Lock-Down features are available on special order.
️· CMP Bit Dependency: Block protection behavior heavily relies on the CMP bit settings. Refer to the datasheet for the detailed interaction between CMP and BP bits.
️· Security Registers: The Security Registers are protected by the LB bit.

Bit	Name	Description
S15	SUS	Erase/Program Suspend status
S14	CMP	CMP bit. Affects block protection behavior.
S13	HPF	High Performance Flag. Indicates High Performance Mode.
S12	Reserved	Reserved bit.
S11	Reserved	Reserved bit.
S10	LB	One-Time Programmable lock for Security Registers.
S9	QE	Quad Enable. Controls Quad mode and WP#/HOLD# pins.
S8	SRP1	Status Register Protection Bit 1.
S7	SRP0	Status Register Protection Bit 0.
S6	BP4	Block Protect bit 4.
S5	BP3	Block Protect bit 3.
S4	BP2	Block Protect bit 2.
S3	BP1	Block Protect bit 1.
S2	BP0	Block Protect bit 0.
S1	WEL	Write Enable Latch.
S0	WIP	Write In Progress.