This document describes the DSPI (Digital Serial Peripheral Interface) Core, a versatile component for serial communication, likely targeted at FPGA or ASIC design. Here's a breakdown of the key information:

1. Overview:

️· Purpose: Provides a flexible and configurable SPI interface.
️· Features: Supports various SPI modes (phase and polarity), error detection, slave select control, and configurable transmission speeds. Designed for compatibility with existing synchronous serial peripherals.
️· Target Devices: Designed to run efficiently on ALTERA® devices.

2. Technical Details:

️· Control Registers: SPI Control Register (SPCR) configures mode of operation, and a Slave Select Control Register (SSCR) manages slave select outputs.
️· Status Register (SPSR): Indicates transfer completion and error conditions.
️· Clock Flexibility: Supports four SPI modes by adjusting the clock phase (CPHA) and polarity (CPOL) bits.
️· Performance: Provides performance details for ALTERA® devices.
️· Transfer Formats: Diagrams illustrating the timing of SPI data transfer for different phase/polarity configurations.
️· Pin Descriptions: A table outlining the purpose and type (input/output) of various pins including global clock (clk), reset (rst), data lines (datai/datao), address lines, control signals (rd/we), and SPI-specific pins (scki, mi, si, ss, datai/datao, irq, scko, sckz, mo, so, ss7o-ss0o).

3. Key Advantages:

️· Configurability: Adaptable to a wide range of SPI applications.

️· Compatibility: Designed for integration into existing designs.
️· Efficient: Optimized for ALTERA® devices.

4. Contact Information:

️· Provides headquarters contact details and a link to a distributor list.



In essence, this document is a technical datasheet for the DSPI Core, detailing its functionality, performance, pinout, and configuration options. It's a valuable resource for engineers looking to incorporate this core into their digital designs.