1. Overview & Purpose

The ADG799A/ADG799G are dual, bidirectional, logic-level CMOS switches designed for I2C bus applications. They allow for multiplexing data between multiple devices and offer bidirectional data flow. Key features include:

· Logic-Level Compatibility: Operates from a wide voltage range (2.7V to 5.5V), making it compatible with common logic levels.
· Bidirectional Switching: Data can flow in either direction through the switches.
· I2C Bus Support: Specifically designed for I2C communication protocols.
· Multiplexing: Allows for connecting multiple devices to a single bus line.
· Low On-Resistance (Ron): Minimizes signal degradation during switching.

2. Key Specifications (Table-Based Summary)

I've consolidated the most important specifications from the various tables (I2C Timing Specifications, Electrical Characteristics). Note that conditions (voltage, temperature) matter!

Specification	Value (Typical/Min/Max)	Units	Notes
Supply Voltage (VDD)	2.7 - 5.5	V	Operating range
Logic-Level Range	1.5 - 5.5	V	Input voltage range for switching
I2C Bus Speed (Standard Mode)	100 kHz
I2C Bus Speed (Fast Mode)	400 kHz
I2C Bus Speed (High Speed Mode)	3.4 MHz
Data Setup Time (t3)	250 ns (Std), 100 ns (FM), 10 ns (HS)	ns	Data must be stable before SCL goes high
Data Hold Time (t42)	0 ns (Std), 3.45 ns (FM), 0 ns (HS)	ns	Data must remain stable after SCL goes low
SDA Rise Time (t9)	1000 ns (Std), 20 + 0.1CB (FM), 300 ns (HS)	ns	dependent on load capacitance (CB)
SCL Rise Time (t11)	Similar to SDA, depends on CB	ns	dependent on load capacitance (CB)
Static On-Resistance (Ron)	Typically < 1 Ω (at VDD = 5V)	Ω	Resistance when switch is ON
Input Leakage Current (IL)	Typically < 1 μA	μA	Current flowing through the switch when OFF
Static Current Consumption (IS)	1 mA (I2C Active Mode)	mA	Typical current draw when switching
Floating State Output Capacitance	~3 pF	pF	When the switch is off, the parasitic capacitance of the switch.
Output Low Voltage, ILOAD = 7mA	< 0.4V	V	Voltage at the output when sinking current

3. I2C Timing Details

· t1 (tHIGH, SCL): High time for the serial clock signal. Minimums are 4 µs (Std), 0.6 µs (FM), 60 ns (HS).
· t2 (tLOW, SCL): Low time for the serial clock signal. Minimums are 4.7 µs (Std), 1.3 µs (FM), 160 ns (HS).
· tSU:DAT (Data Setup Time): The data on the SDA line must be stable *before* the SCL line transitions to a high level. This is crucial for reliable data transfer.
· tHD:DAT (Data Hold Time): The data on the SDA line must remain stable *after* the SCL line transitions to a low level.
· CB: Load capacitance. Important for calculating rise and fall times of the SDA and SCL lines. It impacts the maximum achievable bus speed.

4. Key Considerations & Design Tips

· Load Capacitance (CB): Carefully consider the capacitance on the I2C bus lines. This significantly impacts the maximum achievable bus speed. Use smaller capacitance whenever possible.
· Pull-up Resistors: Properly sized pull-up resistors on the SDA and SCL lines are essential for I2C bus operation. The value of the pull-up resistors depends on the capacitance and the desired bus speed.
· Noise Immunity: The I2C bus is susceptible to noise. Good PCB layout techniques (short traces, ground planes) can help improve noise immunity.