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EPM7160E Datasheet (PDF) - Altera Corporation

EPM7160E Datasheet PDF - Altera Corporation
Part # EPM7160E
Download  EPM7160E Download

File Size   1497.79 Kbytes
Page   66 Pages
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation
Description Programmable Logic Device Family

EPM7160E Datasheet (PDF)

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EPM7160E Datasheet PDF - Altera Corporation

Part # EPM7160E
Download  EPM7160E Click to download

File Size   1497.79 Kbytes
Page   66 Pages
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation
Description Programmable Logic Device Family

EPM7160E Datasheet (HTML) - Altera Corporation

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EPM7160E Product details

General Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.
The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.
In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.

Features...
■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
   – ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available
■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50% in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
   – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
   – Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
■ Enhanced features available in MAX 7000E and MAX 7000S devices
   – Six pin- or logic-driven output enable signals
   – Two global clock signals with optional inversion
   – Enhanced interconnect resources for improved routability
   – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
   – Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
■ Programming support
   – Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices
   – The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices




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About Altera Corporation


Altera Corporation was an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits. It was acquired by Intel Corporation in 2015 and is now a subsidiary of Intel.

Founded in 1983, Altera was one of the pioneers in the field of programmable logic, offering a range of PLD products including field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and specialized chips for digital signal processing and memory interface functions. The company's products were used in a variety of applications including communication systems, industrial automation, medical equipment, and military systems.

Altera was known for its innovation in the PLD market, including the development of high-density FPGAs and low-power, high-performance CPLDs. With its acquisition by Intel, Altera continues to provide PLD solutions for its customers, leveraging the resources and technology of one of the world's largest technology companies.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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