MSP432P411VIPZ datasheet(140/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

6.9.3.1

Timer_A Signal Connection Tables

Table 6-48 to Table 6-51 list the interface signals of the Timer_A modules on the device and connections

of the interface signals to the corresponding pins or internal signals. The following rules apply to the

naming conventions used.

•

The first column lists the device level pin or internal signal that sources the clocks or triggers into the

Timer. The default assumption is that these are pins, unless specifically marked as (internal).

Nomenclature used for internal signals is as follows:

–

CxOUT: Output from Comparator x

–

TAx_Cy: Output from Timer x, Capture/Compare module y

•

The second column lists the input signals of the timer module.

•

The third column lists the submodule of the timer and also implies the functionality [timer, capture

(inputs or triggers), or compare (outputs or PWM)].

•

The fourth column lists the output signals of the timer module.

•

The fifth column lists the device-level pin or internal signal that is driven by the outputs of the timer.

The default assumption is that these are pins, unless specifically marked as (internal).

NOTE

The pin names listed in the tables are the complete names. It is the responsibility of the

software to ensure that the pin is used in the intended mode for the targeted timer

functionality.

NOTE

Internal signals that are sourced by the timer outputs may connect to other modules (for

example, other timers or the ADC) in the device (as trigger sources).

Table 6-48. TA0 Signal Connections

DEVICE INPUT PIN OR INTERNAL

SIGNAL

MODULE INPUT

SIGNAL

MODULE

BLOCK

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT PIN OR

INTERNAL SIGNAL

P7.1/PM_C0OUT/PM_TA0CLK

TACLK

Timer

N/A

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

C0OUT (internal)

INCLK

P7.3/PM_TA0.0

CCI0A

CCR0

TA0

P7.3/PM_TA0.0

TA0_C0 (internal)

DVSS

CCI0B

DVSS

GND

DVCC

VCC

P2.4/PM_TA0.1

CCI1A

CCR1

TA1

P2.4/PM_TA0.1

TA0_C1 (internal)

Precision ADC (internal)

ADC14SHSx = {1}

ACLK (internal)

CCI1B

DVSS

GND

DVCC

VCC

P2.5/PM_TA0.2

CCI2A

CCR2

TA2

P2.5/PM_TA0.2

TA0_C2 (internal)

Precision ADC (internal)

ADC14SHSx = {2}

C0OUT (internal)

CCI2B

DVSS

GND

DVCC

VCC

P2.6/PM_TA0.3

CCI3A

CCR3

TA3

P2.6/PM_TA0.3

TA0_C3 (internal)

C1OUT (internal)

CCI3B

DVSS

GND

DVCC

VCC

MSP432P411VIPZ Datasheet(PDF) 140 Page - Texas Instruments

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