MSP432P411VIPZ datasheet(190/212 Pages) TI1

190 / 212 page

190

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

(1)

X indicates that the value of the control signal or mode of operation has no effect on the functionality.

(2)

This pin is internally pulled up if PJSEL0 is 1.

(3)

The 'default' value in the table indicates the functionality that is selected whenever a hard reset (or higher class reset) occurs.

(4)

This pin is has no internal pull feature. If used in User IO mode or left unused, it must be pulled to GND through an external pulldown

resistor.

(5)

After any hard reset (or higher class reset), this pin returns to TDO functionality with the SWJ in JTAG (4 wire) mode of operation. If

used as a User IO, it reflects the value of the external pullup until the PJSELx bits are reconfigured to the value 00.

6.12.24 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger

Table 6-86 lists the settings to select the port functions.

Table 6-86. Port PJ (PJ.4 to PJ.5) Pin Functions

PIN NAME (P7.x)

FUNCTION

CONTROL BITS OR SIGNALS (1)

SWJ MODE OF

OPERATION (1)

PJDIR.x

PJSEL1.x

PJSEL0.x

PJMAPx

PJ.4/TDI (2)

PJ.4 (I/O)

I: 0; O: 1

TDI

default (3)

JTAG (4 wire)

DVcc

SWD (2 wire)

DVcc

PJ.5/TDO/SWO (4),

(5)

PJ.5 (I/O)

I: 0; O: 1

TDO

default (3)

JTAG (4 wire)

SWO

SWD (2 wire)

Hi-Z

MSP432P411VIPZ Datasheet(PDF) 190 Page - Texas Instruments

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