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C8051F300 Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers

Part # C8051F300
Description  Mixed Signal ISP Flash MCU Family
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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C8051F300/1/2/3/4/5
20
Rev. 2.6
1.2.
On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the
C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and
requires no special off-chip programming voltage. See Figure 1.5 for the C8051F300/1/2/3 system memory
map.
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown)
PROGRAM MEMORY
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
8k bytes
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x1E00
0x1DFF


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