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C8051F300 Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 21 Page - List of Unclassifed Manufacturers |
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21 / 174 page  C8051F300/1/2/3/4/5 Rev. 2.6 21 1.3. On-Chip Debug Circuitry The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, break- points, and single stepping. No additional target RAM, program memory, timers, or communications chan- nels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F300DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a C2 debug adapter. It also has a target application board with the associated MCU installed and large prototyping area, plus the nec- essary communication cables and wall-mount power supply. The Development Kit requires a computer with Windows® 98 SE or later. The Silicon Labs IDE interface is a vastly superior developing and debug- ging configuration, compared to standard MCU emulators that use onboard "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Figure 1.6. Development/In-System Debug Diagram 1.4. Programmable Digital I/O and Crossbar C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. TARGET PCB RS-232 VDD GND C2 (x2), VDD, GND WINDOWS 98 SE or Later Silicon Labs Integrated Development Environment C8051F300 Debug Adapter |
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