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C8051F300 Datasheet(PDF) 38 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 38 Page - List of Unclassifed Manufacturers |
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38 / 174 page  C8051F300/1/2/3/4/5 38 Rev. 2.6 5.3.2. Tracking Modes According to Table 5.1 on page 45, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and- hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track- and-hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling Time Requirements” on page 39. Figure 5.4. 8-Bit ADC Track and Conversion Example Timing Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1 Overflow (AD0CM[2:0]=000, 001, 010, 011) AD0TM=1 Track Convert Low Power Mode AD0TM=0 Track or Convert Convert Track Low Power or Convert SAR Clocks 123 456 789 10 11 12 123 456 789 SAR Clocks B. ADC Timing for Internal Trigger Source 123 456 789 CNVSTR (AD0CM[2:0]=1xx) AD0TM=1 A. ADC Timing for External Trigger Source SAR Clocks Track or Convert Convert Track AD0TM=0 Track Convert Low Power Mode Low Power or Convert |
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