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C8051F300 Datasheet(PDF) 49 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 49 Page - List of Unclassifed Manufacturers |
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49 / 174 page  C8051F300/1/2/3/4/5 Rev. 2.6 49 7. Comparator0 C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull (see Section “12.2. Port I/O Initialization” on page 102). Comparator0 may also be used as a reset source (see Section “9.5. Comparator0 Reset” on page 83). The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1- CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con- figured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “12.3. General Purpose Port I/O” on page 104). Figure 7.1. Comparator0 Functional Block Diagram VDD Reset Decision Tree + - Crossbar Interrupt Logic Q Q SET CLR D Q Q SET CLR D (SYNCHRONIZER) GND CP0 + P0.0 P0.2 P0.4 P0.6 CP0 - P0.1 P0.3 P0.5 P0.7 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 CMX0N1 CMX0N0 CMX0P1 CMX0P0 CP0MD1 CP0MD0 CP0 Rising-edge Interrupt Flag CP0 Falling-edge Interrupt Flag CP0 CP0A |
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