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C8051F300 Datasheet(PDF) 66 Page - List of Unclassifed Manufacturers

Part # C8051F300
Description  Mixed Signal ISP Flash MCU Family
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C8051F300/1/2/3/4/5
66
Rev. 2.6
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
TCON
0x88
Timer/Counter Control
143
TH0
0x8C
Timer/Counter 0 High
146
TH1
0x8D
Timer/Counter 1 High
146
TL0
0x8A
Timer/Counter 0 Low
146
TL1
0x8B
Timer/Counter 1 Low
146
TMOD
0x89
Timer/Counter Mode
144
TMR2RLH
0xCB
Timer/Counter 2 Reload High
150
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
150
TMR2H
0xCD
Timer/Counter 2 High
150
TMR2L
0xCC
Timer/Counter 2 Low
150
XBR0
0xE1
Port I/O Crossbar Control 0
103
XBR1
0xE2
Port I/O Crossbar Control 1
103
XBR2
0xE3
Port I/O Crossbar Control 2
104
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
Reserved
Table 8.3. Special Function Registers* (Continued)
Register
Address
Description
Page
No.
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x82


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