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C8051F300 Datasheet(PDF) 75 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 75 Page - List of Unclassifed Manufacturers |
75 / 174 page C8051F300/1/2/3/4/5 Rev. 2.6 75 SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of the CP0 Rising Edge interrupt. 0: Disable CP0 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP0RIF flag. Bit4: ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt. This bit sets the masking of the CP0 Falling Edge interrupt. 0: Disable CP0 Falling Edge interrupt. 1: Enable interrupt requests generated by the CP0FIF flag . Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. Bit2: EADC0C: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. Bit1: EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag. Bit0: ESMB0: Enable SMBus Interrupt. This bit sets the masking of the SMBus interrupt. 0: Disable all SMBus interrupts. 1: Enable interrupt requests generated by the SI flag. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — ECP0R ECP0F EPCA0 EADC0C EWADC0 ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 |
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