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C8051F300 Datasheet(PDF) 82 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 82 Page - List of Unclassifed Manufacturers |
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82 / 174 page  C8051F300/1/2/3/4/5 82 Rev. 2.6 9.1. Power-On Reset During powerup, the device is held in a reset state and the /RST pin is driven low until VDD settles above VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). For valid ramp times (less than 1 ms), the power-on reset delay (TPORDelay) is typically less than 0.3 ms. Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from reset before VDD reaches the VRST level. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data mem- ory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a power-on reset. Figure 9.2. Power-On and VDD Monitor Reset Timing 9.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD Power-On Reset VDD Monitor Reset /RST t 1.0 2.0 Logic HIGH Logic LOW T PORDelay 2.70 2.55 V RST VDD |
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