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C8051F300 Datasheet(PDF) 93 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 93 Page - List of Unclassifed Manufacturers |
93 / 174 page C8051F300/1/2/3/4/5 Rev. 2.6 93 11. Oscillators C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL reg- isters, as shown in Figure 11.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or a scaled version of the internal oscillator. The internal oscillator's electrical specifica- tions are given in Table 11.1 on page 95. Figure 11.1. Oscillator Diagram 11.1. Programmable Internal Oscillator All C8051F300/1/2/3/4/5 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 11.1. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a 24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may vary ±20% from device-to-device. Electrical specifications for the precision internal oscillator are given in Table 11.1 on page 95. The pro- grammed internal oscillator frequency must not exceed 25 MHz. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg- ister OSCICN. The divide value defaults to 8 following a reset. OSC Programmable Internal Clock Generator Input Circuit EN SYSCLK n OSCICL OSCICN XTAL1 XTAL2 Option 2 VDD XTAL2 Option 1 10M Ω Option 3 XTAL2 Option 4 XTAL2 OSCXCN |
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