RTL8201F/RTL8201FL/RTL8201FN

Datasheet

Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX

vii

Track ID: JATR-2265-11

Rev. 1.4

List of Tables

TABLE 1. MII INTERFACE ..............................................................................................................................................................8

TABLE 2. SERIAL MANAGEMENT INTERFACE ..............................................................................................................................10

TABLE 3. RMII INTERFACE .........................................................................................................................................................10

TABLE 4. CLOCK INTERFACE .......................................................................................................................................................10

TABLE 5. 10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................11

TABLE 6. TRANSMIT BIAS REFERENCE ........................................................................................................................................11

TABLE 7. DEVICE CONFIGURATION INTERFACE...........................................................................................................................11

TABLE 8. POWER AND GROUND PINS ..........................................................................................................................................13

TABLE 9. RESET AND OTHER PINS...............................................................................................................................................14

TABLE 10. NC (NOT CONNECTED) PINS........................................................................................................................................14

TABLE 11. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................15

TABLE 12. REGISTER 1 BASIC MODE STATUS REGISTER...............................................................................................................16

TABLE 13. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................17

TABLE 14. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................17

TABLE 15. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) .....................................................................17

TABLE 16. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................18

TABLE 17. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................19

TABLE 18. PAGE 0 REGISTER 13 MACR (MMD ACCESS CONTROL REGISTER; ADDRESS 0X0D).................................................20

TABLE 19. PAGE 0 REGISTER 14 MAADR (MMD ACCESS ADDRESS DATA REGISTER; ADDRESS 0X0E) ....................................20

TABLE 20. REGISTER 24 POWER SAVING MODE REGISTER (PSMR) .............................................................................................20

TABLE 21. REGISTER 28 FIBER MODE AND LOOPBACK REGISTER ................................................................................................21

TABLE 22. REGISTER 30 INTERRUPT INDICATORS AND SNR DISPLAY REGISTER..........................................................................21

TABLE 23. REGISTER 31 PAGE SELECT REGISTER .........................................................................................................................21

TABLE 24. PAGE4 REGISTER 16 EEE CAPABILITY ENABLE REGISTER ..........................................................................................22

TABLE 25. PAGE4 REGISTER 21 EEE CAPABILITY REGISTER........................................................................................................22

TABLE 26. PAGE7 REGISTER 16 RMII MODE SETTING REGISTER (RMSR)...................................................................................22

TABLE 27. CUSTOMIZED LED MATRIX TABLE .............................................................................................................................23

TABLE 28. PAGE7 REGISTER 17 CUSTOMIZED LEDS SETTING REGISTER .....................................................................................23

TABLE 29. PAGE7 REGISTER 18 EEE LEDS ENABLE REGISTER....................................................................................................23

TABLE 30. PAGE7 REGISTER 19 INTERRUPT, WOL ENABLE, AND LEDS FUNCTION REGISTERS...................................................24

TABLE 31. PAGE7 REGISTER 20 MII TX ISOLATE REGISTER.........................................................................................................25

TABLE 32. PAGE7 REGISTER 24 SPREAD SPECTRUM CLOCK REGISTER ........................................................................................25

TABLE 33. MMD REGISTER MAPPING AND DEFINITION ...............................................................................................................25

TABLE 34. EEEPC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00) ................................................................25

TABLE 35. EEEPS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01)....................................................................26

TABLE 36. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3; ADDRESS 0X14) ...................................................................26

TABLE 37. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3; ADDRESS 0X16).............................................................26

TABLE 38. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7; ADDRESS 0X3C)...........................................................27

TABLE 39. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7; ADDRESS 0X3D) ...........................................27

TABLE 40. MANAGEMENT FRAME FORMAT ..................................................................................................................................29

TABLE 41. SERIAL MANAGEMENT ................................................................................................................................................30

TABLE 42. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC ....................................................................................31

TABLE 43. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................36

TABLE 44. WAKE-ON-LAN PIN TYPES (MII MODE) ....................................................................................................................42

TABLE 45. WAKE-ON-LAN PIN TYPES (RMII MODE)..................................................................................................................42

TABLE 46. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................44

TABLE 47. RECOMMENDED OPERATING CONDITIONS ...................................................................................................................44

TABLE 48. POWER ON AND PHY RESET SEQUENCE......................................................................................................................45

TABLE 49. RMII INPUT MODE POWER DISSIPATION (WHOLE SYSTEM)........................................................................................46

TABLE 50. INPUT VOLTAGE: VCC .................................................................................................................................................46

TABLE 51. MII TRANSMISSION CYCLE TIMING .............................................................................................................................48

TABLE 52. MII RECEPTION CYCLE TIMING ...................................................................................................................................49