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RTL8201CP Datasheet(PDF) 33 Page - Realtek Semiconductor Corp. |
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RTL8201CP Datasheet(HTML) 33 Page - Realtek Semiconductor Corp. |
33 / 37 page ![]() RTL8201CP Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver 28 Track ID: JATR-1076-21 Rev. 1.1 8.2.4. SNI Reception Cycle Timing Table 35. SNI Reception Cycle Timing Symbol Description Minimum Typical Maximum Unit t1 RXCLK high pulse width. 36 ns t2 RXCLK low pulse width. 36 ns t3 RXCLK period. 80 120 ns t4 RXD0 setup to RXCLK rising edge. 40 ns t5 RXD0 hold after RXCLK rising edge. 40 ns t6 Receive frame to CRS high. 50 ns t7 End of receive frame to CRS low. 160 ns t8 Decoder acquisition time. 600 1800 ns Figure 13 shows an example of a packet transfer from PHY to MAC on the SNI interface. Note: SNI mode only runs at 10Mbps. RXCLK RXD0 V IH(min) V IL(max) V IH(min) V IL(max) t4 t 5 t1 t 3 t2 Figure 13. SNI Reception Cycle Timing-1 RXCLK RXD0 CRS TPRX+- t6 t8 t7 Figure 14. SNI Reception Cycle Timing-2 |
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