RTL8201CP datasheet(17/37 Pages) REALTEK

Part #	RTL8201CP

Description	SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER

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Manufacturer	REALTEK [Realtek Semiconductor Corp.]

Direct Link	https://www.realtek.com/en/

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RTL8201CP

Datasheet

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

12

Track ID: JATR-1076-21 Rev. 1.1

6.8. Register 16 NWay Setup Register (NSR)

Table 16. Register 16 NWay Setup Register (NSR)

Address

Name

Description

Mode

Default

16:15~12

Reserved

16:11

ENNWLE

1: LED4 Pin indicates linkpulse

RW

0

16:10

Testfun

1: Auto-negotiation speeds up internal timer

RW

0

16:9

NWLPBK

1: Set NWay to loopback mode.

RW

0

16:8~3

Reserved

16:2

FLAGABD

1: Auto-negotiation experienced ability detect state

RO

0

16:1

FLAGPDF

1: Auto-negotiation experienced parallel detection fault state

RO

0

16:0

FLAGLSC

1: Auto-negotiation experienced link status check state

RO

0

6.9. Register 17 Loopback, Bypass, Receiver Error Mask

Register (LBREMR)

Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)

Address

Name

Description

Mode

Default

17:15

RPTR

Set to 1 to put the RTL8201CP into repeater mode

RW

0

17:14

BP_4B5B

Assertion of this bit allows bypassing of the 4B/5B & 5B/4B

encoder.

RW

0

17:13

BP_SCR

Assertion of this bit allows bypassing of the

scrambler/descrambler.

RW

0

17:12

LDPS

Set to 1 to enable Link Down Power Saving mode

RW

0

17:11

AnalogOFF

Set to 1 to power down analog function of transmitter and

receiver.

RW

0

17:10

Reserve

Reserved.

17:9

LB

Set to 1 to enable DSP Loopback.

RW

0

17:8

F_Link_10

Used to logic force good link in 10Mbps for diagnostic purposes.

RW

1

17:7

F_Link_100

Used to logic force good link in 100Mbps for diagnostic purposes.

RW

1

17:6

JBEN

Set to 1 to enable Jabber Function in 10Base-T

RW

0

17:5

CODE_err

Assertion of this bit causes a code error detection to be reported.

RW

0

17:4

PME_err

Assertion of this bit causes a pre-mature end error detection to be

reported.

RW

0

17:3

LINK_err

Assertion of this bit causes a link error detection to be reported.

RW

0

17:2

PKT_err

Assertion of this bit causes a ‘detection of packet errors due to

722 ms time-out’ to be reported.

RW

0

17:1

FXMODE

This bit indicates whether Fiber Mode is Enabled.

RO

0

17:0

RMIIMODE

This bit indicates whether RMII mode is Enabled.

RO

0

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RTL8201CP Datasheet(PDF) 17 Page - Realtek Semiconductor Corp.

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