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RTL8101L Datasheet(PDF) 3 Page - Realtek Semiconductor Corp. |
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RTL8101L Datasheet(HTML) 3 Page - Realtek Semiconductor Corp. |
3 / 96 page RTL8101L Datasheet Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management iii Track ID: JATR-1076-21 Rev. 1.5 Table of Contents 1. GENERAL DESCRIPTION................................................................................................................................................1 2. FEATURES...........................................................................................................................................................................2 2.1. ETHERNET CONTROLLER FEATURES ...............................................................................................................................2 2.2. MC’97 CONTROLLER FEATURES.....................................................................................................................................3 3. SYSTEM APPLICATIONS ................................................................................................................................................3 4. BLOCK DIAGRAM.............................................................................................................................................................4 5. PIN ASSIGNMENTS ...........................................................................................................................................................5 5.1. PACKAGE IDENTIFICATION..............................................................................................................................................5 6. PIN DESCRIPTIONS ..........................................................................................................................................................6 6.1. POWER MANAGEMENT/ISOLATION INTERFACE ...............................................................................................................6 6.2. PCI INTERFACE ...............................................................................................................................................................7 6.3. EEPROM INTERFACE .....................................................................................................................................................8 6.4. POWER PINS ....................................................................................................................................................................9 6.5. LED INTERFACE..............................................................................................................................................................9 6.6. ATTACHMENT UNIT INTERFACE......................................................................................................................................9 6.7. AC-LINK PINS...............................................................................................................................................................10 6.8. TEST AND OTHER PINS ..................................................................................................................................................10 7. ETHERNET CONTROLLER REGISTER DESCRIPTIONS ......................................................................................11 7.1. RECEIVE STATUS REGISTER IN RX PACKET HEADER....................................................................................................14 7.2. TRANSMIT STATUS REGISTER (TSD0-3)(OFFSET 0010H-001FH, R/W)........................................................................14 7.3. ERSR: EARLY RX STATUS REGISTER (OFFSET 0036H, R)............................................................................................16 7.4. COMMAND REGISTER (OFFSET 0037H, R/W) ................................................................................................................17 7.5. INTERRUPT MASK REGISTER (OFFSET 003CH-003DH, R/W) ........................................................................................18 7.6. INTERRUPT STATUS REGISTER (OFFSET 003EH-003FH, R/W) ......................................................................................19 7.7. TRANSMIT CONFIGURATION REGISTER (OFFSET 0040H-0043H, R/W)..........................................................................20 7.8. RECEIVE CONFIGURATION REGISTER (OFFSET 0044H-0047H, R/W)............................................................................22 7.9. 9346CR: 93C46 COMMAND REGISTER (OFFSET 0050H, R/W).....................................................................................25 7.10. CONFIG 0: CONFIGURATION REGISTER 0 (OFFSET 0051H, R/W)............................................................................26 |
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