RTL8111C-GR

Datasheet

Integrated Gigabit Ethernet Controller for PCI Express

iii

Track ID: JATR-1076-21

Rev. 1.1

Table of Contents

1.

General Description .................................................................................................... 1

2.

Features ........................................................................................................................2

3.

System Applications .................................................................................................... 2

4.

Pin Assignments........................................................................................................... 3

4.1. PACKAGE IDENTIFICATION ...............................................................................................................3

5.

Pin Descriptions........................................................................................................... 4

5.1. POWER MANAGEMENT/ISOLATION...................................................................................................4

5.2. PCI EXPRESS INTERFACE .................................................................................................................4

5.3. EEPROM.........................................................................................................................................5

5.4. TRANSCEIVER INTERFACE ................................................................................................................5

5.5. CLOCK..............................................................................................................................................6

5.6. REGULATOR & REFERENCE..............................................................................................................6

5.7. LEDS ...............................................................................................................................................6

5.8. POWER & GROUND...........................................................................................................................7

5.9. GPIO................................................................................................................................................7

5.10. NC (NOT CONNECTED) PINS ............................................................................................................7

6.

Functional Description................................................................................................ 8

6.1. PCI EXPRESS BUS INTERFACE..........................................................................................................8

6.1.1.

PCI Express Transmitter.........................................................................................................................................8

6.1.2.

PCI Express Receiver .............................................................................................................................................8

6.2. LED FUNCTIONS ..............................................................................................................................8

6.2.1.

Link Monitor...........................................................................................................................................................8

6.2.2.

Rx LED ...................................................................................................................................................................9

6.2.3.

Tx LED ...................................................................................................................................................................9

6.2.4.

Tx/Rx LED ............................................................................................................................................................10

6.2.5.

LINK/ACT LED .................................................................................................................................................... 11

6.3. PHY TRANSCEIVER........................................................................................................................12

6.3.1.

PHY Transmitter ...................................................................................................................................................12

6.3.2.

PHY Receiver........................................................................................................................................................12

6.4. NEXT PAGE ....................................................................................................................................13

6.5. EEPROM INTERFACE ....................................................................................................................13

6.6. POWER MANAGEMENT ...................................................................................................................14

6.7. VITAL PRODUCT DATA (VPD) .......................................................................................................16

6.8. MESSAGE SIGNALED INTERRUPT (MSI) .........................................................................................17

6.8.1.

MSI Capability Structure in PCI Configuration Space.........................................................................................17

6.8.2.

Message Control...................................................................................................................................................18

6.8.3.

Message Address ..................................................................................................................................................18

6.8.4.

Message Upper Address .......................................................................................................................................19

6.8.5.

Message Data .......................................................................................................................................................19

6.9. MSI-X............................................................................................................................................20

6.9.1.

MSI-X Capability Structure in PCI Configuration Space.....................................................................................20