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RTL8201N-GR Datasheet(PDF) 6 Page - Realtek Semiconductor Corp.

Part # RTL8201N-GR
Description  SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8201N-GR Datasheet(HTML) 6 Page - Realtek Semiconductor Corp.

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RTL8201N
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
vi
Rev. 1.1
List of Figures
Figure 1. Block Diagram .............................................................................................................................3
Figure 2. Pin Assignments...........................................................................................................................4
Figure 3. Read Cycle .................................................................................................................................16
Figure 4. Write Cycle ................................................................................................................................16
Figure 5. MII Transmission Cycle Timing-1.............................................................................................26
Figure 6. MII Transmission Cycle Timing-2.............................................................................................26
Figure 7. MII Reception Cycle Timing-1 ..................................................................................................27
Figure 8. MII Reception Cycle Timing-2 ..................................................................................................27
Figure 9. SNI Transmission Cycle Timing-1 ............................................................................................28
Figure 10. SNI Transmission Cycle Timing-2 ............................................................................................28
Figure 11. SNI Reception Cycle Timing-1..................................................................................................29
Figure 12. SNI Reception Cycle Timing-2..................................................................................................29
Figure 13. MDC/MDIO Timing ..................................................................................................................30
Figure 14. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................30
Figure 15. MDC/MDIO PHY to MAC Reception Without Error ...............................................................31


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