RTL8201N &RTL8201R

Datasheet

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

with Auto MDIX

vii

Track ID: JATR-1076-21 Rev. 1.3

List of Figures

FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3

FIGURE 2. RTL8201N-GR (64-PIN QFN) PIN ASSIGNMENTS .......................................................................................................4

FIGURE 3. RTL8201R-GR (32-PIN QFN) PIN ASSIGNMENTS........................................................................................................5

FIGURE 4. READ CYCLE...............................................................................................................................................................19

FIGURE 5. WRITE CYCLE .............................................................................................................................................................19

FIGURE 6. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................29

FIGURE 7. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................29

FIGURE 8. MII RECEPTION CYCLE TIMING-1...............................................................................................................................30

FIGURE 9. MII RECEPTION CYCLE TIMING-2...............................................................................................................................30

FIGURE 10. RMII TRANSMISSION CYCLE TIMING .........................................................................................................................31

FIGURE 11. RMII RECEPTION CYCLE TIMING ...............................................................................................................................31

FIGURE 12. SNI TRANSMISSION CYCLE TIMING-1 ........................................................................................................................32

FIGURE 13. SNI TRANSMISSION CYCLE TIMING-2 ........................................................................................................................32

FIGURE 14. SNI RECEPTION CYCLE TIMING-1 ..............................................................................................................................33

FIGURE 15. SNI RECEPTION CYCLE TIMING-2 ..............................................................................................................................33

FIGURE 16. MDC/MDIO TIMING..................................................................................................................................................34

FIGURE 17. MAC TO PHY TRANSMISSION WITHOUT COLLISION ..................................................................................................34

FIGURE 18. PHY TO MAC RECEPTION WITHOUT ERROR ..............................................................................................................35