Approval Sheet

Page 7 of 14

ASC_RMASMU890ATF03_V02

Nov. 2017

Note 1 : Input SDATA is sampled at the falling edge of the SCLK.

Note 2 : Output SDATA changes at the rising edge of the SCLK.

Note 3 : The time between the consecutive Register Write Command Sequences for the Switch State register.

Note 4 : The time for the switch to reach Active State.

Note : The table of input SCLK signal conditions as below.

Parameter

Symbol

Ratings

Unit

SCLK Frequency

Full Speed

0.032 to 26

MHz

Half Speed

0.032 to 13

SCLK Period

Full Speed

0.038 to 32

μs

Half Speed

0.077 to 32

SCLK Rise/Fall Time

Full/Half Speed

3.5 to 6.5

ns

SCLK Input Duty Cycle,

High/Low Time

50

%

AC Waveforms

SCLK(IN)

SDATA(IN)

Tr

Tf

VIO

GND

VIO

GND

Tr

Tf

SCLK(IN)

VIO

GND

Bus Park Cycle

VIO

GND

SDATA(OUT)