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STR720 Datasheet(PDF) 106 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 106 Page - STMicroelectronics |
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106 / 401 page  STR720 - DRAM CONTROLLER (DRAMC) 106/401 Bank 4 Configuration Register (MB4Config) Address Offset: 0Ch Reset value: 0000h The Bank 4 Configuration Register (MB4Config) is a 16-bit read/write control register used to configure specific parameters of external region 4 (Bank 4). The MB4Config control bits are the same as MB1Config register. Bank 1 SDRAM Configuration Register Low (SDRAM1ConfigLo) Address Offset: 10h Reset value: 0000h The Bank 1 SDRAM Configuration Register Low (SDRAM1ConfigLo) is a 16-bit write only control register used to configure the SDRAM device of external region 1 (Bank 1). The SDRAM1ConfigLo control bits are described below. Bit 15:14 reserved (should be written as zero ). Bit 13:0 MIAB[13:0]: Memory Interface Address Bus. This field defines the data to be written in the SDRAM internal configuration register by directly driving the SDRAM address bus lines. They will be asserted on the SDRAM address bus with the value written in SDRAM1ConfigLo register for one clock period. 15 14 13 12 11 10 9 8 7 6543210 reserved DEVWID[1:0] DATALAT[1:0] SETUPTIME[2:0] IDLETIME[2:0] SDRAMCOL[1:0] rw rw rw rw rw 15 14 13 12 11 10 9 8 765432 1 0 reserved MIAB wo 1 |
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