STR720 datasheet(135/401 Pages) STMICROELECTRONICS

Part #	STR720

Description	ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

PDF	401 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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135 / 401 page

STR720 - ATAPI-IDE INTERFACE

135/401

Bits 13:12 = ISPP: IOrdy Sample Point.

Defines how many clock periods before Iordry is sampled, 00=5, 01=4, 10=3, 11=2

Bit 14 = STEN: Slave IDE Timing Enable

0: Disable Slave IDE Timing. RCTP and ISPP configurations apply to both Drives 0/1

1: Enable Slave IDE Timing. RCTP and ISPP configurations apply to just Drive 0. To configure

Drive 1 RCTP and ISPP settings, use the SLIDETIM register.

Bit 15 = DCDEN: IDE Decode Enable

0: Disable IDE Decode

1: Enable IDE Decode

Slave IDE Timing (SLIDETIM)

Address Offset: 144h

Reset value: 00h

Bits 1:0 = RCTS: Primary Drive 1 Recovery Time.

Defines the minimum number of clock periods NIRD/NIWR are inactive between successive

cycles: 00=4, 01=3, 10=2, 11=1. Note that bit 14 (STEN) of PIDETIM must be set to 1 for

these settings to take effect.

Bits 3:2 = ISPS: Primary Drive 1 IOrdy Sample Point.

Defines how many clock periods after NIRD/NIWR is asserted on the IDE before IOrdy is

sampled: 00=5, 01=4, 10=3, 11=2. Note that bit 14 (STEN) of PIDETIM must be set to 1 for

these settings to take effect.

Bits 7:4 = Reserved. Must be kept at reset value.

Reserved

ISPS

RCTS

-rw

STR720 Datasheet(PDF) 135 Page - STMicroelectronics