HDMP-1636A Transceiver

HDMP-1646A Transceiver

HDMP-T1636A Transceiver

Features

• IEEE 802.3z Gigabit Ethernet

Compatible

• ANSI x3.230-1994 Fibre

Channel Compatible (FC-O)

• Supports Serial Data Rates of

1062.5 MBd (Fibre Channel)

& 1250 MBd (Gigabit

Ethernet)

• Low Power Consumption,

630 mW Typical

• Transmitter and Receiver

Functions Incorporated onto

a Single IC

• Three Package Sizes

Available:

– 10 mm TQFP (HDMP-T1636A)

– 10 mm PQFP (HDMP-1636A)

– 14 mm PQFP (HDMP-1646A)

• 10-Bit Wide Parallel TTL

Compatible I/Os

• Single +3.3 V Power Supply

• 5-Volt Tolerant I/Os

• 2 kV ESD Protection on All

Pins

Applications

• 1250 MBd Gigabit Ethernet

Interface

• 1062.5 MBd Fibre Channel

Interface

• Mass Storage System I/O

Channel

• Work Station/Server I/O

Channel

• Backplane Serialization

• FC Interface for Disk Drives

and Arrays

Gigabit Ethernet and

Fibre Channel SerDes ICs

Technical Data

Description

The HDMP-1636A/46A/T1636A

transceiver is a single integrated

circuit packaged in a plastic QFP

package. It provides a low-cost,

low-power physical layer solution

for 1250 MBd Gigabit Ethernet,

1062.5 MBd Fibre Channel, and

proprietary link interfaces. It

provides complete Serialize/

Deserialize (SerDes) for copper

transmission, incorporating the

Gigabit Ethernet/Fibre Channel

transmit and receive functions

into a single device.

This chip is used to build a high

speed interface (as shown in

Figure 1) while minimizing board

space, power and cost. It is

compatible with the IEEE 802.3z

specification.

The transmitter section accepts

10-bit wide parallel TTL data and

serializes this data into a high

speed serial data stream. The

parallel data is expected to be

“8B/10B” encoded data, or equiv-

alent. This parallel data is latched

into the input register of the

transmitter section on the rising

edge of the reference clock (used

as the transmit byte clock). A

1062.5 MHz reference clock is

used in Fibre Channel operation,

whereas a 125 MHz reference

clock is used in Gigabit Ethernet

operation.

The transmitter section’s PLL

locks to the user supplied

reference byte clock. This clock

is then multiplied by 10 to gener-

ate the high speed serial clock

used to generate the high speed

output. The high speed outputs

are capable of interfacing directly

to copper cables for electrical

transmission or to a separate

fiber optic module for optical

transmission.

The receiver section accepts a

serial electrical data stream at

1062.5 MBd or 1250 MBd and

recovers the original 10-bit wide

parallel data. The receiver PLL

locks onto the incoming serial

signal and recovers the high

speed serial clock and data. The

serial data is converted back into

10-bit parallel data, recognizing

the 8B/10B comma character to

establish byte alignment.

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).