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RTL8111F-CG Datasheet(PDF) 10 Page - Realtek Semiconductor Corp. |
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RTL8111F-CG Datasheet(HTML) 10 Page - Realtek Semiconductor Corp. |
10 / 37 page RTL8111F Datasheet Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-2265-11 Rev. 1.1 5. Pin Descriptions The signal type codes below are used in the following tables: I: Input S/T/S: Sustained Tri-State O: Output O/D: Open Drain T/S: Tri-State bi-directional input/output pin P: Power 5.1. Power Management/Isolation Table 1. Power Management/Isolation Symbol Type Pin No Description LANWAKEB O/D 28 Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. ISOLATEB I 26 Isolate Pin: Active low. Used to isolate the RTL8111F from the PCI Express bus. The RTL8111F will not drive its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI Express input as long as the Isolate pin is asserted. 5.2. PCI Express Interface Table 2. PCI Express Interface Symbol Type Pin No Description REFCLK_P I 19 REFCLK_N I 20 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm. HSOP O 22 HSON O 23 PCI Express Transmit Differential Pair. HSIP I 17 HSIN I 18 PCI Express Receive Differential Pair. PERSTB I 25 PCI Express Reset Signal: Active low. When the PERSTB is asserted at power-on state, the RTL8111F returns to a pre-defined reset state and is ready for initialization and configuration after the de-assertion of the PERSTB. CLKREQB O/D 16 Reference Clock Request Signal. This signal is used by the RTL8111F to request starting of the PCI Express reference clock. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. |
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