STM8S datasheet(254/467 Pages) STMICROELECTRONICS

254 / 467 page

8-bit basic timer (TIM4, TIM6)

RM0016

254/467

DocID14587 Rev 14

19.2

TIM4 main features

The main features include:

•

8-bit auto-reload up counter

•

3-bit programmable prescaler which allows dividing (also “on the fly”) the counter clock

frequency by 1, 2, 4, 8, 16, 32, 64 and 128.

•

Interrupt generation

–

On counter update: Counter overflow

19.3

TIM6 main features

The main features include:

•

8-bit auto-reload up counter

•

3-bit programmable prescaler which allows dividing (also “on the fly”) the counter clock

frequency by 1, 2, 4, 8, 16, 32, 64 and 128.

•

Synchronization circuit to control the timer with external signals and to interconnect

several timers (See Section 17.4.6 on page 159).

•

Interrupt generation

–

On counter update: Counter overflow

–

On trigger input

19.4

TIM4/TIM6 interrupts

The timer has 2 interrupt request sources:

•

Update interrupt (overflow, counter initialization)

•

Trigger input (TIM6 only)

19.5

TIM4/TIM6 clock selection

The clock source for the timer is the internal clock (fMASTER). It is connected directly to the

CK_PSC clock that feeds the prescaler driving the counter clock CK_CNT.

Prescaler

The prescaler implementation is as follows:

•

The prescaler is based on a 7-bit counter controlled through a 3-bit register (in the

TIMx_PSCR register). It can be changed on the fly as this control register is buffered. It

can divide the counter clock frequency by any power of 2 from 1 to 128.

The counter clock frequency is calculated as follows:

fCK_CNT = fCK_PSC/2(PSCR[2:0])

The prescaler value is loaded through a preload register. The shadow register, which

contains the current value to be used, is loaded as soon as the LS byte has been written.

Read operations to the TIMx_PSCR registers access the preload registers, so no special

care needs to be taken to read them.

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