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STM32F722VCK6TR Datasheet(PDF) 160 Page - STMicroelectronics |
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STM32F722VCK6TR Datasheet(HTML) 160 Page - STMicroelectronics |
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160 / 229 page ![]() Electrical characteristics STM32F722xx STM32F723xx 160/229 DS11853 Rev 6 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 50 or Figure 51, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. STM32 1 μF // 10 nF 1 μF // 10 nF VREF+ (1) VDDA VSSA/VREF+ (1) ai17535c STM32F 1 μF // 10 nF ai17536c VREF+/VDDA VREF-/VSSA (1) (1) |
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