STM32F722VCK6TR datasheet(171/229 Pages) STMICROELECTRONICS

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DS11853 Rev 6

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STM32F722xx STM32F723xx

Electrical characteristics

201

SAI characteristics

Unless otherwise specified, the parameters given in Table 83 for SAI are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 16, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C=30 pF

•

Measurement points are performed at CMOS levels: 0.5VDD

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate

function characteristics (SCK,SD,WS).

Table 83. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCKL

SAI Main clock output

256x8K

256xFs

MHz

FCK

SAI clock frequency(2)

Master data: 32 bits

128xFs(3)

Slave data: 32 bits

128xFs(3)

tv(FS)

FS valid time

Master mode

2.7≤VDD≤3.6V

-18

Master mode

1.71≤VDD≤3.6V

-20

tsu(FS)

FS setup time

Slave mode

th(FS)

FS hold time

Master mode

Slave mode

0.5

tsu(SD_A_MR)

Data input setup time

Master receiver

tsu(SD_B_SR)

Slave receiver

2.5

th(SD_A_MR)

Data input hold time

Master receiver

3.5

th(SD_B_SR)

Slave receiver

0.5

tv(SD_B_MT)

Data output valid time

Slave transmitter (after enable edge)

2.7≤VDD≤3.6V

-11

Slave transmitter (after enable edge)

1.71≤VDD≤3.6V

-18

th(SD_B_ST)

Data output hold time

Slave transmitter (after enable edge)

tv(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7≤VDD≤3.6V

-16

Master transmitter (after enable edge)

1.71≤VDD≤3.6V

-18.5

th(SD_A_MT)

Data output hold time

Master transmitter (after enable edge)

7.5

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With Fs = 192 KHz.

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