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ADIS16489 Datasheet(PDF) 28 Page - Analog Devices |
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ADIS16489 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 40 page  ADIS16489 Data Sheet Rev. B | Page 28 of 40 On Demand Self Test (ODST) Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD[1] = 1 (DIN = 0x8202, then DIN = 0x8300) to run the ODST routine, which executes the following steps: 1. Measure the output on each sensor. 2. Activate an internal force on the mechanical elements of each sensor, which simulates the force associated with actual inertial motion. 3. Measure the output response on each sensor. 4. Deactivate the internal force on each sensor. 5. Calculate the difference between the force on and normal operating conditions (force off). 6. Compare the difference with internal pass/fail criteria. 7. Report the pass/fail results for each sensor in DIAG_STS (see Table 18) and the overall pass/fail flag in SYS_E_FLAG[5] (see Table 16). When using an external clock, the self test execution times may vary from the 12 ms listed in Table 1. Also, false positive results are possible when the executing the ODST while the device is in motion. Bias Correction Update Turn to Page 3 (DIN = 0x8003) and set GLOB_CMD[0] = 1 (DIN = 0x8201, then DIN = 0x8300) to update the user offset registers with the correction factors of the continuous bias estimator (CBE). Ensure that the inertial platform is stable during the entire average time for optimal bias estimates. AUXILIARY I/O LINE CONFIGURATION (FNCTIO_CTRL) Table 152. FNCTIO_CTRL Register Definitions Page Addresses Default Access Flash Backup 0x03 0x06, 0x07 0x000D R/W Yes Table 153. FNCTIO_CTRL Bit Definitions Bits Description [15:12] Not used 11 Alarm indicator: 1 = enabled, 0 = disabled 10 Alarm indicator polarity: 1 = positive, 0 = negative [9:8] Alarm indicator line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 7 Sync clock input enable: 1 = enabled, 0 = disabled 6 Sync clock input polarity: 1 = rising edge, 0 = falling edge [5:4] Sync clock input line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 3 Data ready enable: 1 = enabled, 0 = disabled 2 Data ready polarity: 1 = positive, 0 = negative [1:0] Data ready line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 The FNCTIO_CTRL register (see Table 152 and Table 153) provides configuration control for each input/output pin (DIO1, DIO2, DIO3, and DIO4). Each DIOx pin supports only one function at a time. In cases where a single pin has two assignments, the enable bit for the lower priority function automatically resets to zero (disabling the lower priority function). The order of priority is as follows, from highest priority to lowest priority: data ready, sync clock input, alarm indicator, and general purpose. Changing the FNCTIO_ CTRL[5:4] bit settings requires an execution time of 75 ms, whereas changing the settings of the remaining bits in the FNCTIO_CTRL register only takes 3 ms. During this execution time (75 ms or 3 ms), the operational state and the contents of the register remain unchanged, but the SPI interface supports normal communication (for accessing other registers). Data Ready Indicator The FNCTIO_CTRL[3:0] bits provide three configuration options for the data ready function: on/off, polarity, and DIOx line. The primary purpose this signal is to drive the interrupt control line of an embedded processor, which can help synchronize data collection and minimize latency. The factory default assigns DIO2 as a positive polarity data ready signal, which means that the data in the output registers is valid when the DIO2 line is high (see Figure 31). This configuration works well when DIO2 drives an interrupt service pin that activates on a low to high pulse. DIO2 ACTIVE INACTIVE Figure 31. Data Ready, When FNCTIO_CTRL[3:0] = 1101 (default) Use the following sequence to change this assignment to DIO1 with a negative polarity: 1. Turn to Page 3 (DIN = 0x8003). 2. Set FNCTIO_CTRL[3:0] = 1000 (DIN = 0x8608, then DIN = 0x8700). The timing jitter on the pulse width of the data ready signal is typically ±1.4 µs. Input Sync/Clock Control FNCTIO_CTRL[7:4] provide configuration options for using one of the DIOx lines as an input synchronization signal for sampling inertial sensor data. For example, use the following sequence to establish DIO4 as a positive polarity input clock pin and keep the factory default setting for the data ready function: 1. Turn to Page 3 (DIN = 0x8003). 2. Set FNCTIO_CTRL[7:0] = 0xFD (DIN = 0x86FD). 3. Set FNCTIO_CTRL[15:8] = 0x00 (DIN = 0x8700). This command also disables the internal sampling clock. Therefore, no data sampling occurs if no input clock signal is present. The best performance is available when using an input clock frequency of 2400 Hz. |
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