DSPIC30F2012 datasheet(161/207 Pages) MICROCHIP

161 / 207 page

Preliminary

DS70139C-page 159

dsPIC30F2011/2012/3012/3013

TABLE 20-16: INTERNAL CLOCK TIMING EXAMPLES

TABLE 20-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature

-40°C

≤ TA ≤ +85°C for Industrial

-40°C

≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic(1)

Min

Typ(2)

Max

Units

Conditions

OS50

FPLLI

PLL Input Frequency Range(2)

—

MHz

EC, XT modes with PLL

OS51

FSYS

On-chip PLL Output(2)

—

120

MHz

EC, XT modes with PLL

OS52

TLOC

PLL Start-up Time (Lock Time)

—

μs

OS53

DCLK

CLKOUT Stability (Jitter)

TBD

Measured over 100 ms

period

Note 1:

These parameters are characterized but not tested in manufacturing.

Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

Clock

Oscillator

Mode

FOSC

(MHz)(1)

TCY (

μsec)(2)

MIPS(3)

w/o PLL

MIPS(3)

w PLL x4

MIPS(3)

w PLL x8

MIPS(3)

w PLL x16

0.200

20.0

0.05

—

1.0

4.0

8.0

16.0

0.4

2.5

10.0

20.0

—

0.16

6.25

—

1.0

4.0

8.0

16.0

0.4

2.5

10.0

20.0

—

Note 1:

Assumption: Oscillator Postscaler is divide by 1.

Instruction Execution Cycle Time: TCY = 1 / MIPS.

Instruction Execution Frequency: MIPS = (FOSC * PLLx) / 4 [since there are 4 Q clocks per instruction

cycle].

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