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DSPIC30F2012 Datasheet(PDF) 174 Page - Microchip Technology |
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DSPIC30F2012 Datasheet(HTML) 174 Page - Microchip Technology |
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174 / 207 page  dsPIC30F2011/2012/3012/3013 DS70139C-page 172 Preliminary © 2005 Microchip Technology Inc. FIGURE 20-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS TABLE 20-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. Symbol Characteristic(1)(2) Min Typ(3) Max Units Conditions CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns — CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns — CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to Falling Edge of BIT_CLK —— 10 ns — CS66 THACL Input Hold Time from Falling Edge of BIT_CLK —— 10 ns — CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — μs Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — μs Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — μs Note 1 CS75 TRACL Rise Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS76 TFACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS77 TRACL Rise Time, SYNC, SDATA_OUT — TBD TBD ns CLOAD = 50 pF, VDD = 3V CS78 TFACL Fall Time, SYNC, SDATA_OUT — TBD TBD ns CLOAD = 50 pF, VDD = 3V CS80 TOVDACL Output valid delay from rising edge of BIT_CLK —— 15 ns — Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. SYNC BIT_CLK SDO SDI CS61 CS60 CS65 CS66 CS80 CS21 MSb IN CS75 LSb CS76 (COFS) (CSCK) LSb MSb CS72 CS71 CS70 CS76 CS75 (CSDO) (CSDI) CS62 CS20 |
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