LTC4450

10

Rev. 0

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Layout Considerations

High current applications demand careful attention

to trace resistances. The PCB trace associated with the IN/

OUT pins should have low resistance to reduce conduc-

tion power loss. Keep the traces to the IN and OUT pins

wide and short to minimize resistive losses. To ensure

a low contact resistance, solder the device’s IN/OUT

pins to the board using a reflow process. Include holes

underneath the exposed pads to keep solder in place to

APPLICATIONS INFORMATION

Figure 6. Recommended Layout

avoid high voltage shorts between pins. The wide IN/OUT

traces also act as a heat sink to remove the heat in the

pressors and necessary transient protection components

close to the LTC4450 using short lead lengths. Transient

voltage suppressors should have short wide traces to

pins. Figure 6 shows the recommended PCB layout for

the LTC4450. The temperature rise of the recommended

PCB layout with 6A load current is 25°C.

GND

GND

GND

OPTIONAL

TVS OR SCHOTTKY

1

2

3

4

5

6

VCC

IN

IN

IN

IN

IN

14

13

12

11

10

9

GND

OUT

OUT

OUT

OUT

OUT

16

15

7

8

4450 F06