| Electronic Components Datasheet Search |
|
PCIMX6DP5EYM2AB Datasheet(PDF) 112 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCIMX6DP5EYM2AB Datasheet(HTML) 112 Page - NXP Semiconductors |
|
112 / 166 page ![]() i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 112 NXP Semiconductors Electrical Characteristics 4.12.12.6 High-Speed Clock Timing Figure 69. DDR Clock Definition 4.12.12.7 Forward High-Speed Data Transmission Timing The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in Figure 70: Figure 70. Data to Clock Timing Definitions 4.12.12.8 Reverse High-Speed Data Transmission Timing Figure 71. Reverse High-Speed Data Transmission Timing at Slave Side LS Equivalent wire bond series inductance — — — 1.5 nH RS Equivalent wire bond series resistance — — — 0.15 Ω RL Load Resistance — 80 100 125 Ω Table 69. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit 1 Data Bit Time = 1UI UIINST(1) 1 Data Bit Time = 1UI UIINST(2) CLKp CLKn 1 DDR Clock Period = UIINST(1) + UIINST(2) TTD 2UI 2UI CLKp CLKn Clock to Data Skew NRZ Data |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |