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PCIMX6DP7AYM2AB Datasheet(PDF) 116 Page - NXP Semiconductors |
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PCIMX6DP7AYM2AB Datasheet(HTML) 116 Page - NXP Semiconductors |
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116 / 160 page  i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 116 NXP Semiconductors Electrical Characteristics 4.12.17 SCAN JTAG Controller (SJC) Timing Parameters Figure 80 depicts the SJC test clock input timing. Figure 81 depicts the SJC boundary scan timing. Figure 82 depicts the SJC test access port. Figure 83 depicts the JTAG_TRST_B timing. Signal parameters are listed in Table 70. Figure 80. Test Clock Input Timing Diagram Figure 81. Boundary Scan (JTAG) Timing Diagram JTAG_TCK (Input) VM VM VIH VIL SJ1 SJ2 SJ2 SJ3 SJ3 JTAG_TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid Output Data Valid SJ4 SJ5 SJ6 SJ7 SJ6 |
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