CY3LV512/010
PRELIMINARY
Document #: 38-03002 Rev. *A
Page 2 of 9
Functional Description
The CY3LV512/010 (high-density CY3LV Series) CPLD boot
EEPROMs provide an easy-to-use, cost-effective configura-
tion memory for Complex Programmable Logic Devices. The
CY3LV Series is packaged in the popular 20-pin PLCC. These
devices support a system-friendly READY pin, which signifies
a “good” power level to the CPLD and can be used to ensure
reliable system power-up.
The CY3LV Series boot PROMs can be programmed with in-
dustry-standard programmers or Cypress’s CYDH2200E
CPLD boot PROM programming kit. Please refer to the data
sheet “CYDH2200E CPLD Boot PROM Programming Kit” for
details.
CPLD Master Serial Mode Summary
The I/O and logic functions of the CPLD and their associated
interconnections are established by loading configuration data
(bitstream) into the CPLD. This configuration data is loaded
either automatically upon power-up, or upon issuing JTAG-
command. The configuration data is stored in the internal
Flash memory (Self-Boot packages only) or in the external
CPLD boot PROM memory. This data is loaded from the ap-
propriate memory depending on the state of the CPLD mode
select pin (MSEL).
In Master Serial mode (when MSEL=1), the CPLD automati-
cally loads the configuration program from an external memo-
ry i.e., CY3LV CPLD boot PROM. These PROMs have been
designed for compatibility with the Master Serial Mode. This
document discusses the interface between Cypress’s SRAM
based CPLDs (Quantum38K and Delta39K) and CY3LV
PROMs.
For more details on the other modes of configuration of these
CPLDs please refer to the application note titled “Configuring
Delta39K/Quantum38K.”
Controlling the CY3LV CPLD Boot PROMs
During Configuration
Most connections between the CPLD device and the CY3LV
boot PROM are simple and self-explanatory. Figure 1 shows
the
five
signal
interface
required
between
the
Delta39K/Quantum38K CPLD and the CY3LV boot PROM
device.
• The DATA output of the boot PROM drives DATA input of
the CPLD
• The master CPLD CCLK output drives the CLK input of the
boot PROM
• The CPLD CCE pin drives the CE input of the boot PROM
• The RESET/OE input of the boot PROM is driven by the
CPLD RESET pin
• The READY pin of the boot PROM is connected to the RE-
CONFIG pin of the CPLD
The READY pin is available as an open-collector indicator of
the device’s RESET status; it is driven LOW while the device
is
in
its
POWER-ON
RESET
cycle
and
released
(three-stated) when the cycle is complete. The rising edge of
the READY (hence RECONFIG) signal causes the CPLD to
start configuring. The CONFIG_DONE, CCE and RESET out-
put of the CPLD are set LOW, CCLK is activated and CPLD
starts receiving configuration data on the DATA pin. After all
the configuration data is shifted in, the CPLD device deacti-
vates the CCLK and sets CCE, RESET and CONFIG_DONE
HIGH.
A HIGH level on the RESET/OE input — during CPLD reset
— clears the boot PROM’s internal address pointer and sub-
sequent reconfiguration starts at the beginning.
The CEO output of any CY3LV drives the CE input of the next
CY3LV in a cascade chain of EEPROMs.
SER_EN must be connected to VCC, (except during In-System
Programming).
Figure 1. Interface between Delta39K/Quantum38K CPLD and CY3LV boot PROM
4.7K
Ω
V
CC
TCLK
TMS
TDI
TDO
Config_Done
Reconfig
GND
CCLK
CCE
Reset
DATA
DATA
CE
Reset/OE
CLK
V
CC
GND
3.3V
DELTA39K/
QUANTUM38K
SER_EN
V
CCJTAG
V
CCPRG
V
CCCNFG
V
CCIO
V
CC
V
CCIO
CY3LV512/010
MSEL
READY
V
CCPLL
1K
Ω
1
µF
0.1
µF
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