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STM32L071VB Datasheet(PDF) 146 Page - STMicroelectronics |
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STM32L071VB Datasheet(HTML) 146 Page - STMicroelectronics |
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146 / 148 page ![]() Revision history STM32L071xx 146/148 DS10690 Rev 7 14-Sep-2017 4 Memories and I/Os moved after Core in Features. Table 2: Ultra-low-power STM32L071xx device features and peripheral counts: changed number of USART for LQFP32/UFQFPN32 and added note 3. Removed column "I/O operation" from Table 3: Functionalities depending on the operating power supply range and added note related to GPIO speed. In Section 5: Memory mapping, replaced memory mapping schematic by reference to the reference manual. Update note related to PA11/12 below Figure 3: STM32L071xx LQFP100 pinout, Figure 4: STM32L071xx UFBGA100 ballout, Figure 5: STM32L071xx LQFP64 pinout, Figure 6: STM32L071xx UFBGA64/TFBGA64 ballout, Figure 7: STM32L071xx WLCSP49 ballout, Figure 8: STM32L071xx LQFP48 pinout and Figure 11: STM32L071xx UFQFPN32 pinout. Updated Figure 7: STM32L071xx WLCSP49 ballout. Added mission profile compliance with JEDEC JESD47 in Section 6.2: Absolute maximum ratings. Removed CRS from Table 39: Peripheral current consumption in Run or Sleep mode. Updated minimum and maximum values of I/O weak pull-up equivalent resistor (RPU) and weak pull-down equivalent resistor (RPD) in Table 58: I/O static characteristics. Updated minimum and maximum values of NRST weak pull-up equivalent resistor (RPU) in Table 61: NRST pin characteristics. Added note 2. related to the position of the external capacitor below Figure 29: Recommended NRST pin protection. Updated RAIN in Table 62: ADC characteristics. Updated tAF maximum value for range 1 in Table 70: I2C analog filter characteristics. Removed Table 90: USART/LPUART characteristics. NSS timing waveforms updated in Figure 34: SPI timing diagram - slave mode and CPHA = 0 and Figure 35: SPI timing diagram - slave mode and CPHA = 1(1). Updated Figure 49: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline. Added reference to optional marking or inset/upset marks in all package device marking sections. Updated note below marking schematics. Table 90. Document revision history (continued) Date Revision Changes |
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