STM32469VG datasheet(121/220 Pages) STMICROELECTRONICS

121 / 220 page

DS11189 Rev 7

121/220

STM32F469xx

Electrical characteristics

191

tLOCK

PLL lock time

VCO frequency = 192 MHz

200

µs

VCO frequency = 432 MHz

100

300

Jitter(3)

Cycle-to-cycle jitter

System clock

120 MHz

RMS

peak to peak

150

Period jitter

RMS

peak to peak

200

Main clock output (MCO) for RMII

Ethernet

Cycle to cycle at 50 MHz on

1000 samples

-32-

Main clock output (MCO) for MII

Ethernet

Cycle to cycle at 25 MHz on

1000 samples

-40-

Bit time CAN jitter

Cycle to cycle at 1 MHz on

1000 samples

330

IDD(PLL)(4)

PLL power consumption on VDD

VCO frequency = 192 MHz

VCO frequency = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLL)(4)

PLL power consumption on VDDA

VCO frequency = 192 MHz

VCO frequency = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of two PLLs in parallel can degrade the jitter up to +30%.

4. Based on test during characterization.

Table 41. Main PLL characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 42. PLLI2S (audio PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLI2S_IN

PLLI2S input clock(1)

-0.95(2)

12.10

MHz

fPLLI2S_OUT

PLLI2S multiplier output

clock

216

fVCO_OUT

PLLI2S VCO output

192

432

tLOCK

PLLI2S lock time

VCO frequency = 192 MHz

200

µs

VCO frequency = 432 MHz

100

300

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on 48KHz

period, N=432, R=5

RMS

peak to peak

280

Average frequency of 12.288 MHz,

N=432, R=5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

400

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