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STM32469VG Datasheet(PDF) 127 Page - STMicroelectronics |
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STM32469VG Datasheet(HTML) 127 Page - STMicroelectronics |
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127 / 220 page  DS11189 Rev 7 127/220 STM32F469xx Electrical characteristics 191 Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram 5.3.14 MIPI D-PHY PLL characteristics The parameters given in Table 47 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. MS38282V1 Clock Lane Data Lane TLPX THS-PREPARE TCLK-PRE TCLK-ZERO TCLK-PREPARE TLPX THS-EXIT TCLK-TRAIL TCLK-POST VIL VIL TEOT MS38283V1 Clock Lane THS-PREPARE TLPX THS-TRAIL THS-EXIT LP-01 LP-00 LP-11 Data Lane VIL TREOT TEOT THS-ZERO Table 47. DSI-PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 4 - 100 MHz fPLL_INFIN PFD input clock - 4 - 25 fPLL_OUT PLL multiplier output clock - 31.25 - 500 fVCO_OUT PLL VCO output - 500 - 1000 tLOCK PLL lock time - - - 200 µs |
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