STM32469VG datasheet(217/220 Pages) STMICROELECTRONICS

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DS11189 Rev 7

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STM32F469xx

Recommendations when using internal reset OFF

217

Appendix A

Recommendations when using internal reset

OFF

When the internal reset is OFF, the following integrated features are no longer supported:



The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.



The brownout reset (BOR) circuitry must be disabled.



The embedded programmable voltage detector (PVD) is disabled.



VBAT functionality is no more available and VBAT pin should be connected to VDD.



The over-drive mode is not supported.

A.1

Operating conditions

Table 125. Limitations depending on the operating power supply range

Operating

power

supply

range

ADC

operation

Maximum Flash

memory access

frequency with no

wait states (fFlashmax)

Maximum

Flash memory

access frequency

with wait states (1)(2)

I/O operation

Possible

Flash memory

operations

VDD =1.7 to

2.1 V(3)

Conversion

time up to

1.2 Msps

20 MHz(4)

168 MHz with 8 wait

states and over-drive

OFF

– No I/O

compensation

8-bit erase and

program

operations only

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is

required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the

execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state

program execution.

3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 2.19.1: Internal

reset ON).

4. Prefetch is not available. Refer to AN3430, available on www.st.com, for details on how to adjust performance and power.

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