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AD9361BBCZ-REEL Datasheet(PDF) 5 Page - Analog Devices |
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AD9361BBCZ-REEL Datasheet(HTML) 5 Page - Analog Devices |
5 / 36 page ![]() Data Sheet AD9361 Rev. F | Page 5 of 36 Parameter1 Symbol Min Typ Max Unit Test Conditions/ Comments TX MONITOR INPUTS (TX_MON1, TX_MON2) Maximum Input Level 4 dBm Dynamic Range 66 dB Accuracy 1 dB LO SYNTHESIZER LO Frequency Step 2.4 Hz 2.4 GHz, 40 MHz reference clock Integrated Phase Noise 800 MHz 0.13 ° rms 100 Hz to 100 MHz, 30.72 MHz reference clock (doubled internally for RF synthesizer) 2.4 GHz 0.37 ° rms 100 Hz to 100 MHz, 40 MHz reference clock 5.5 GHz 0.59 ° rms 100 Hz to 100 MHz, 40 MHz reference clock (doubled internally for RF synthesizer) REFERENCE CLOCK (REF_CLK) REF_CLK is either the input to the XTALP/XTALN pins or a line directly to the XTALN pin Input Frequency Range 19 50 MHz Crystal input 10 80 MHz External oscillator Signal Level 1.3 V p-p AC-coupled external oscillator AUXILIARY CONVERTERS ADC Resolution 12 Bits Input Voltage Minimum 0.05 V Maximum VDDA1P3_BB − 0.05 V DAC Resolution 10 Bits Output Voltage Minimum 0.5 V Maximum VDD_GPO − 0.3 V Output Current 10 mA DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High VDD_INTERFACE × 0.8 VDD_INTERFACE V Low 0 VDD_INTERFACE × 0.2 V Input Current High −10 +10 μA Low −10 +10 μA Logic Outputs Output Voltage High VDD_INTERFACE × 0.8 V Low VDD_INTERFACE × 0.2 V DIGITAL SPECIFICATIONS (LVDS) Logic Inputs Input Voltage Range 825 1575 mV Each differential input in the pair Input Differential Voltage Threshold −100 +100 mV Receiver Differential Input Impedance 100 Ω |
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