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DVR Datasheet(PDF) 218 Page - Microchip Technology |
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DVR Datasheet(HTML) 218 Page - Microchip Technology |
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218 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 218 2016-2018 Microchip Technology Inc. FIGURE 17-3: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Serial Transmit FIFO (SPIxTXB)(2) Shift Register (SPIxTXSR) LSb MSb SDIx SDOx Processor 2 (SPIx Slave) SCKx SSx(1) Serial Receive FIFO (SPIxRXB)(2) Serial Receive FIFO (SPIxRXB)(2) Shift Register (SPIxRXSR) MSb LSb SDOx SDIx Processor 1 (SPIx Master) Serial Clock MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0 SCKx Serial Transmit FIFO (SPIxTXB)(2) MSTEN (SPIxCON1L<5>) = 1 SPIx Buffer (SPIxBUF) SPIx Buffer (SPIxBUF) Shift Register (SPIxTXSR) Shift Register (SPIxRXSR) MSb LSb LSb MSb SDOx SDIx Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF. |
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