DVR21 datasheet(214/416 Pages) MICROCHIP

214 / 416 page

PIC24FJ256GA705 FAMILY

DS30010118D-page 214

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SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW

U-0

R/W-0

U-0

R/W-0

—

FRMERREN

BUSYEN

—

SPITUREN

bit 15

bit 8

R/W-0

U-0

R/W-0

U-0

R/W-0

SRMTEN

SPIROVEN

SPIRBEN

—

SPITBEN

—

SPITBFEN

SPIRBFEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

Unimplemented: Read as ‘0’

bit 12

FRMERREN: Enable Interrupt Events via FRMERR bit

1 = Frame error generates an interrupt event

0 = Frame error does not generate an interrupt event

bit 11

BUSYEN: Enable Interrupt Events via SPIBUSY bit

1 = SPIBUSY generates an interrupt event

0 = SPIBUSY does not generate an interrupt event

bit 10-9

Unimplemented: Read as ‘0’

bit 8

SPITUREN: Enable Interrupt Events via SPITUR bit

1 = Transmit Underrun (TUR) generates an interrupt event

0 = Transmit Underrun does not generate an interrupt event

bit 7

SRMTEN: Enable Interrupt Events via SRMT bit

1 = Shift Register Empty (SRMT) generates interrupt events

0 = Shift Register Empty does not generate interrupt events

bit 6

SPIROVEN: Enable Interrupt Events via SPIROV bit

1 = SPIx Receive Overflow generates an interrupt event

0 = SPIx Receive Overflow does not generate an interrupt event

bit 5

SPIRBEN: Enable Interrupt Events via SPIRBE bit

1 = SPIx Receive Buffer Empty generates an interrupt event

0 = SPIx Receive Buffer Empty does not generate an interrupt event

bit 4

Unimplemented: Read as ‘0’

bit 3

SPITBEN: Enable Interrupt Events via SPITBE bit

1 = SPIx Transmit Buffer Empty generates an interrupt event

0 = SPIx Transmit Buffer Empty does not generate an interrupt event

bit 2

Unimplemented: Read as ‘0’

bit 1

SPITBFEN: Enable Interrupt Events via SPITBF bit

1 = SPIx Transmit Buffer Full generates an interrupt event

0 = SPIx Transmit Buffer Full does not generate an interrupt event

bit 0

SPIRBFEN: Enable Interrupt Events via SPIRBF bit

1 = SPIx Receive Buffer Full generates an interrupt event

0 = SPIx Receive Buffer Full does not generate an interrupt event

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