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DVR21 Datasheet(PDF) 236 Page - Microchip Technology |
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DVR21 Datasheet(HTML) 236 Page - Microchip Technology |
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236 / 416 page ![]() PIC24FJ256GA705 FAMILY DS30010118D-page 236 2016-2018 Microchip Technology Inc. bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect) 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (the character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (the character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’-to-‘0’ transition) will reset the receive buffer and the RSR to the empty state) bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN = 1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. |
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