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C8051F121 Datasheet(PDF) 1 Page - Silicon Laboratories |
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C8051F121 Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 2 page  Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004 P0, P1, P2, P3 Latches JTAG Logic TCK TMS TDI TDO UART1 SMBus SPI Bus PCA 256 B RAM VDD Monitor SFR Bus 8 0 5 1 C o r e Timers 0, 1, 2, 4 Timer 3 P0 Drv C R O S S B A R VDD VDD VDD DGND DGND DGND AV+ AGND Reset RST XTAL1 XTAL2 External Oscillator Circuit System Clock Internal 2% Oscillator Digital Power Analog Power Debug HW Boundary Scan 8 kB XRAM P2.0 P2.7 P1.0/AIN1.0 P1.7/AIN1.7 P0.0 P0.7 P1 Drv P2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 (12-Bit) VREF DAC0 (12-Bit) ADC 100 ksps (12-Bit) A M U X AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 DAC0 CP0+ CP0- CP1+ CP1- VREF TEMP SENSOR UART0 P3.0 P3.7 P3 Drv Prog Gain ADC 500 ksps (8-Bit) A M U X 8:1 MONEN WDT VREFA Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV External Data Memory Bus N/M PLL REFADC VDD REFADC 128 kB FLASH 256 Byte Branch Target Buffer Prefetch HW 32 8 16 x 16 Mult/Acc (2-cycle) C8051F121 100 MIPS, 128 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals 12-Bit ADC - ±1 LSB INL; no missing codes - Programmable throughput up to 100 ksps - 8 external inputs; programmable as single-ended or differential - Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 - Data-dependent windowed interrupt generator - Built-in temperature sensor (±3 °C) 8-Bit ADC - ±1 LSB INL; no missing codes - Programmable throughput up to 500 ksps - 8 external inputs - Programmable amplifier gain: 4, 2, 1, 0.5 Two 12-Bit DACs - Can synchronize outputs to timers for jitter-free waveform generation Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, watchpoints, stack monitor - Inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - IEEE1149.1 compliant boundary scan High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 100 MIPS throughput with 100 MHz system clock - 16 x 16 multiply/accumulate engine (2-cycle) Memory - 8448 bytes data RAM - 128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) - External parallel data memory interface Digital Peripherals - 32 port I/O; all are 5 V tolerant - Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently - Programmable 16-bit counter/timer array with six capture/compare modules - 5 general-purpose 16-bit counter/timers - Dedicated watchdog timer; bidirectional reset - Real-time clock mode using Timer 3 or PCA Clock Sources - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation - On-chip programmable PLL: up to 100 MHz - External oscillator: Crystal, RC, C, or Clock Supply Voltage: 3.0 to 3.6 V - Typical operating current: 50 mA at 100 MHz - Typical stop mode current: 0.4 uA 64-Pin TQFP Temperature Range: –40 to +85 °C |
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