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FT801 Datasheet(PDF) 15 Page - Bridgetek Pte Ltd.

Part # FT801
Description  Embedded Video Engine
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Manufacturer  BRIDGETEK [Bridgetek Pte Ltd.]
Direct Link  https://brtchip.com/
Logo BRIDGETEK - Bridgetek Pte Ltd.

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FT801 Embedded Video Engine Datasheet
Version 1.3
Document Reference No.: BRT_000001
Clearance No.: BRT#003
4.2.2 Phase Locked Loop
The internal PLL takes input clock from the oscillator, and generates clocks to all internal circuits,
including graphics engine, audio engine and touch engine.
4.2.3 Clock Enable
Upon power-on the FT801 enters standby mode. The internal relaxation oscillator is selected for the PLL
clock source. The system clock will be enabled when following step is executed:
Host sends an “ACTIVE” command (dummy read at address 0)
If the application choose to use the external clock source (12MHz crystal or clock), the following steps
shall be executed:
Host sends an “ACTIVE” command (dummy read at address 0)
Host sends an “CLKEXT” command
Host writes to REG_PCLK with non-zero value (i.e. 5)
If SPI is used as host interface, the SPI clock shall not exceed 11MHz before system clock is enabled.
After system clock is properly enabled, the SPI clock is allowed to go up to 30MHz.
4.2.4 Clock Frequency
Upon power-on the internal relaxation oscillator is untrimmed. The frequency range could be quite wide
from chip to chip (refer to table x-y for internal relaxation oscillator specifications). If the application
utilises the internal clock without external clock source, it is recommended to perform clock trimming by
software for better performance. For the details of clock trimming mechanism please refer to application
note AN_299 FT800 FT801 Internal Clock Trimming.
By default the system clock is 48MHz when the input clock is 12MHz. Host is allowed to switch the system
clock between 48MHz and 36MHz by the host command “CLK48MHz” and “CLK36MHz” respectively. The
clock switching is synchronised to VSYNC edge on the fly. This is to avoid possible graphics glitch during
clock switching. As a result, the clock switch will only take effect if the REG_PCLK is a non-zero value.
4.3
Graphics Engine
4.3.1 Introduction
The graphics engine executes the display list once for every horizontal line. It executes the primitive
objects in the display list and constructs the display line buffer. The horizontal pixel content in the line
buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
The primitive objects supported by the graphics processor are: lines, points, rectangles, bitmaps
(comprehensive set of formats), text display, plotting bar graph, edge strips, and line strips, etc.
Operations such as stencil test, alpha blending and masking are useful for creating a rich set of
effects such as shadows, transitions, reveals, fades and wipes.
Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer.
Bitmap transformations enable operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics states
Tag buffer detection
The graphics engine also supports customized build-in widgets and functionalities such as jpeg decode,
screen saver, calibration etc. The graphics engine interprets commands from the MPU host via a 4 Kbyte
FIFO in FT801 memory at RAM_CMD. The MPU/MCU writes commands into the FIFO, and the graphics
engine reads and executes the commands. The MPU/MCU updates register REG_CMD_WRITE to indicate
that there are new commands in the FIFO, and the graphics engine updates REG_CMD_READ after
commands have been executed.


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