KSZ9567RTXI-TR datasheet(187/232 Pages) MICROCHIP

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 2017-2019 Microchip Technology Inc.

DS00002329D-page 187

KSZ9567R

5.2.11.11

Port PTP Timestamp Interrupt Enable Register

5.2.11.12

Port PTP Link Delay Register

Address:

0xNC16 - 0xNC17

Port N: 1-7

Size:

16 bits

Bits

Description

Type

Default

Port N Egress Timestamp for Sync Frame Interrupt Enable

(TS_SYNC_INT_ENB)

When this bit is set to 1, the egress timestamp interrupt from Port N for the

Sync frame is enabled.

This bit is logical OR’ed together with the rest of the bits in this register and

the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask

R/W

Port N Egress Timestamp for Pdelay_Req and Delay_Req Frames

Interrupt Enable (TS_PDLY_REQ_INT_ENB)

When this bit is set to 1, the egress timestamp interrupt from Port N for the

Pdelay_Req and Delay_Req frames is enabled.

This bit is logical OR’ed together with the rest of the bits in this register and

the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask

R/W

Port N Egress Timestamp for Pdelay_Resp Frame Interrupt Enable

(TS_PDLY_RESP_INT_ENB)

When this bit is set to 1, the egress timestamp interrupt from Port N for the

Pdelay_Resp frame is enabled.

This bit is logical OR’ed together with the rest of the bits in this register and

the output is shown as the PTP Interrupt Enable bit in the Port Interrupt Mask

R/W

12:0

RESERVED

0x000

Address:

0xNC18 - 0xNC1B

Port N: 1-7

Size:

32 bits

Bits

Description

Type

Default

31:0

PTP Port N Link Delay in nanoseconds

This register is used to set the link delay value between port N and the link

partner port.

R/W

0x0000_0000

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