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QB-R5F100SL-TB Datasheet(PDF) 147 Page - Renesas Technology Corp |
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QB-R5F100SL-TB Datasheet(HTML) 147 Page - Renesas Technology Corp |
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147 / 207 page  RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 147 of 200 Jun 30, 2020 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/12 Note 1 bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.6 Mbps 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/12 Note 1 bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.6 Mbps 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/12 Notes 1,2 bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.6 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. |
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